The present invention relates to stress testing for microprocessors and other agents in a computer system. More specifically, the present invention relates to an on-die validation functional unit block (“FUB”) provided in an agent such as a microprocessor.
In a computer system, an “agent” may include any device that communicates with other devices via a common communication bus using a common bus interface protocol. Typical agents include microprocessors, memory controllers, bridge interface circuits, digital signal processors and application specific integrated circuits. As can be appreciated, a modern agent may include several hundreds of thousands of transistors fabricated into a single integrated circuit. Although circuit designs are simulated before the circuit designs are fabricated in an operable integrated circuit, validation testing is necessary to ensure that the integrated circuit actually behaves in practice as the design intends.
Validation testing includes stress testing. Stress testing involves pushing the operating conditions of an agent to its performance limits to determine that the agent's actual behavior matches simulated predictions. Stress testing, however, is a costly, complicated hit-or-miss process because it traditionally is performed through software-controlled algorithms. When an integrated circuit is manufactured, traditional stress testing requires that the integrated circuit execute program instructions that are designed to place the agent in a predetermined condition of stress. For example, software may be written to cause two different processors to continually read and modify data at the same memory location. By creating contention between the two processors, it provides an opportunity for validation personnel to observe the behavior of the processors as they compete over the same piece of data. Of course, the precise instant when the desired stress event occurs cannot be predicted. Thus, diagnostic personnel must observe thousands of bus transactions to determine when (sometimes, if) the stress event occurs. Not only is it expensive to design stress-testing software, it is expensive to review and interpret stress testing results.
Software-controlled algorithms do not provide much control at all. To test the functioning of external bus logic, the circuitry within an agent that controls the agent's interface to the external bus, it is desirable to maintain a sustained level of high traffic on the bus. Software-controlled algorithms can be interrupted by context switches by the operating system and other events. This can lower the level of traffic on the bus. Additionally, there is no way to software-controlled algorithms cannot respond to events on the external bus sufficiently quickly to guarantee that timing relationships can be maintained on the bus to test certain bus events. Indeed, there are many events that validation engineers would like to test that cannot be sensed by software at all. All of these issues reduce the efficiency of validation testing through software.
Accordingly, there is a need in the art for an improved validation testing scheme for use in a processor or other agent.